From 0932d2e226db8345f92375fb4b81cfc26bc00197 Mon Sep 17 00:00:00 2001 From: zcwBit Date: Tue, 30 May 2023 16:08:47 +0800 Subject: [PATCH] =?UTF-8?q?0530=E6=9B=B4=E6=96=B0?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- protocol/FF/FFSimulate.py | 2 +- protocol/Hart/HartSimulate.py | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/protocol/FF/FFSimulate.py b/protocol/FF/FFSimulate.py index c2cfbc8..a41b2ab 100644 --- a/protocol/FF/FFSimulate.py +++ b/protocol/FF/FFSimulate.py @@ -8,7 +8,7 @@ import modbus_tk.defines as cst class FFSimulate(object): def __init__(self): - self.rtuSlave = RTUSlave(port = 'COM10', baudrate = 9600, bytesize = 8, parity = 'N', stopbits = 1, xonxoff = 0) + self.rtuSlave = RTUSlave(port = 'COM12', baudrate = 9600, bytesize = 8, parity = 'N', stopbits = 1, xonxoff = 0) self.AIAddr = [x for x in range(4100, 4107) if x % 2 == 0] self.AOAddr = [x for x in range(4200, 4207) if x % 2 == 0] self.DIAddr = [x for x in range(4300, 4304)] diff --git a/protocol/Hart/HartSimulate.py b/protocol/Hart/HartSimulate.py index 4162cfa..2dd7e8a 100644 --- a/protocol/Hart/HartSimulate.py +++ b/protocol/Hart/HartSimulate.py @@ -8,7 +8,7 @@ import modbus_tk.defines as cst class HartSimulate(object): def __init__(self): - self.rtuSlave = RTUSlave(port = 'COM7', baudrate = 9600, bytesize = 8, parity = 'E', stopbits = 1, xonxoff = 0) + self.rtuSlave = RTUSlave(port = 'COM11', baudrate = 9600, bytesize = 8, parity = 'E', stopbits = 1, xonxoff = 0) self.varAddrList = [x for x in range(4100, 4107) if x % 2 == 0] self.spanAddrList = [4200, 4202] self.writeList = self.varAddrList + self.spanAddrList